Kiran Patel

Ph.D. student at the University of Illinois at Chicago (UIC)

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Welcome! I am Kiran Patel, a second year Ph.D. student at UIC in the Electrical and Computer Engineering department where I am advised by Prof. Brent Stephens. I am broadly interested in computer architecture with particular emphasis on hardware design, FPGA development, and on-chip networks. As a part of my research I am currently focusing on the design of FPGA based programmable NICs and leverage FPGA cores to enable new network protocols, services, and offloads.


Work Experience

Teaching Assistant

University of Illinois at Chicago, Illinois USA | Fall 2019

Freshman level, ECE 311 Communication Engineering | Lecturer: Prof. Besma Smida

Faculty Member

Dept. of Electronics & Telecom Engg | 2016 - 2017

National Institute of Technology, Raipur, C.G. India

Teaching Assistant

Embedded System and Real Time Lab | 2015 - 2016

National Institute of Technology, Rourkela, Odisha India

Projects

Follow-up work on: Your Programmable NIC Should be a Programmable Switch, a.k.a., PANIC

UIC | Spring 2019 - Present

I am currently working on the follow-up work for PANIC, a new programmable NIC design under HotNets-2018-PANIC: Your Programmable NIC Should be a Programmable Switch. As a part of this work, we are trying to investigate the design of high throughput on-chip packet routing networks for programmable NICs and determining the performance characteristics and the energy and chip area costs of different on-chip network designs for a programmable NIC.

Classification of Handwritten Digits using ML

UIC | Fall 2018

Implemented a linear classifier on Intel DE1-SoC FPGA board to classify images of numbers ranging between 0 to 9. The ten class classification task was implemented in OpenCL language and the design was executed on FPGA with an accuracy of 90.87%.

Hardware Architecture of Image de-noising model

NIT Rourkela, India | 2014-16

Implemented the hardware architecture of Image de-noising model using Discrete Wavelet Transform (DWT) with the help of ‘Lifting Scheme’ technique in ModelSim and MATLAB software. Tested the implementation of CDF 5⁄3 hardware and denoising procedure but with lower time complexity.

Information

About me

  • I completed my Masters of Technology in Electrical Engineering from National Institute of Technology, (NIT), Rourkela, where I specialized in Hardware architecture of Image processing models. I have a strong will to build a career in academia hence I joined the National Institute of Technology, (NIT), Raipur as a faculty member in the Electronics and Telecommunication department. After spending a little time over there, I joined UIC as a doctoral student under the guidance of Prof. Brent Stephens where we are trying to build new architectures for Network Interface Cards (NICs) and reconfigurable match table (RMT) switches.

Interests

Besides research, I enjoy doing modern calligraphy and handlettering. Thanks for reading!