Kiran Patel

Kiran Patel

Ph.D. student

University of Illinois at Chicago

Biography

Welcome! I am Kiran Patel, a Ph.D. student at UIC in the Electrical and Computer Engineering department where I am advised by Prof. Brent Stephens. I am broadly interested in computer architecture with particular emphasis on hardware design, FPGA development, and on-chip networks. As a part of my research I am currently focusing on the design of FPGA based programmable NICs and leverage FPGA cores to enable new network protocols, services, and offloads.

Education

  • PhD, Spring 2019 - Present

    University of Illinois at Chicago

  • M.Tech, 2014-2016

    National Institute of Technology, Rourkela, India

  • B.E., 2009-2013

    Shri Shankaracharya College of Engg. and Tech., India

Experience

 
 
 
 
 

Research Assistant

University of Illinois at Chicago

Sep 2019 – Present
I am working with Prof. Brent Stephens on a new programmable NIC design
 
 
 
 
 

Teaching Assistant

University of Illinois at Chicago

Sep 2019 – Dec 2019
Freshman level, ECE 311 Communication Engineering with Prof. Besma Smida
 
 
 
 
 

Faculty Member

National Institute of Technology, Raipur

Jun 2016 – Feb 2017 India
Department of Electronics and Telecommunication Engineering
 
 
 
 
 

Teaching Assistant

National Institute of Technology, Rourkela

Sep 2015 – Jun 2016 India
Embedded Systems and Real-time lab

Projects

Follow-up work on Your Programmable NIC Should be a Programmable Switch, a.k.a., PANIC

I am currently working on the follow-up work for PANIC, a new programmable NIC design under HotNets-2018-PANIC: Your Programmable NIC Should be a Programmable Switch. As a part of this work, we are trying to investigate the design of high throughput on-chip packet routing networks for programmable NICs and determining the performance characteristics and the energy and chip area costs of different on-chip network designs for a programmable NIC.

On-Chip Network Congestion control

I am studying the On-chip congestion control for existing multiple different Smart-NICs and consequences of congestion in terms of latency and packet-drop.

Wavelet based Image Denoising Model

Implemented the hardware architecture of Image de-noising model using Discrete Wavelet Transform (DWT) with the help of ‘Lifting Scheme’ technique in ModelSim and MATLAB software. Tested the implementation of CDF 5⁄3 hardware and denoising procedure but with lower time complexity.

Contact